This invention relates to nonvolatile semiconductor memory devices and, more particularly, to electrically-erasable, electrically-programmable, read-only memories (EEPROMs) having floating-gate-type memory cells and to a method for making such devices.
Currently available nonvolatile memories require a programming voltage of about +18 V to write data into the floating gates of memory cells. In particular, a voltage pulse having a peak value of about +18 V is applied to the control gate of a cell during programming while the source of the cell is at 0 V. Application of the +18 V to the control gate causes unnecessarily high electric field stresses in circuits external to the memory array, such as the wordline driver circuitry.
There is a need for a nonvolatile memory array that permits the circuitry outside of the memory array to be constructed for use at lower voltages and decreased electric field stress. Such an array would allow external circuitry, such as wordline driver circuits, to be built with thinner gate oxides and with smaller dimensions, if operated at lower voltages. The smaller dimensions would allow a decrease in the size of the external circuitry to correspond to the continuing decrease in the size of memory cells.